Patents by Inventor James R. Janesick

James R. Janesick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Back side thinned CCD with high speed channel stop
Patent number: 6369415
Abstract: A back thinned CCD has at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.
Type: Grant
Filed: December 22, 1999
Date of Patent: April 9, 2002
Assignee: Pixel Vision, Inc.
Inventor: James R. Janesick

CCD based optical detector for a confocal microscope
Patent number: 5844598
Abstract: An optical detector includes a charge-coupled device (CCD). The CCD comprises an active cell for receiving a narrow beam of incident illumination and generating photoelectrons in response thereto, and a first stage readout register comprising a row of N transfer cells, where N>1. A first stage gate structure transfers charge packets consecutively from the active cell into the first stage readout register, whereby N successive charge packets are read into the N cells respectively of the first stage readout register. N second stage readout registers each comprise M transfer cells, where M>1, and a second stage gate structure transfers N charge packets from the N cells of the first stage readout register into respective first cells of the second stage readout registers and subsequently shifts the N charge packets from the respective first cells of the second stage readout registers to respective Mth cells thereof.
Type: Grant
Filed: January 17, 1996
Date of Patent: December 1, 1998
Assignee: Pixel Vision, Inc.
Inventor: James R. Janesick

Frontside illuminated charge-coupled device with high sensitivity to the blue, ultraviolet and soft X-ray spectral range
Patent number: 5365092
Abstract: A CCD which is designed and processed so that most of each pixel is covered only with an ultra-thin gate electrode so that the CCD can be frontside illuminated and still achieve good sensitivity in the ultra-violet and soft x-ray spectral range. More specifically, in the present invention, the usual three gate structure and corresponding polysilicon layers 1, 2 and 3 of conventional thickness are reduced in width and supplemented by a fourth ultra-thin layer of polysilicon dubbed herein, poly 4, that is deposited over the entire array. This fourth layer, poly 4, makes contact with poly 3, so that when poly 3 is driven, it also drives poly 4, thus allowing charge to collect and transfer as in a normal three phase CCD. However, because the deposition thickness of the poly 4 layer is on the order of 400 Angsttoms, as opposed to conventional thicknesses of 2000 to 5000 Angsttoms, poly 4 is essentially transparent to photons and thereby allows achievement of high quantum efficiency.
Type: Grant
Filed: February 8, 1993
Date of Patent: November 15, 1994
Assignee: California Institute of Technology
Inventor: James R. Janesick

Ultra low-noise charge coupled device
Patent number: 5250824
Abstract: Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively.
Type: Grant
Filed: May 11, 1992
Date of Patent: October 5, 1993
Assignee: California Institute of Technology
Inventor: James R. Janesick

Front-illuminated CCD with open pinned-phase region and two-phase transfer gate regions
Patent number: 5077592
Abstract: A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.
Type: Grant
Filed: August 6, 1990
Date of Patent: December 31, 1991
Assignee: California Institute of Technology
Inventor: James R. Janesick

CCD imaging sensor with flashed backside metal film
Patent number: 5005063
Abstract: A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning.
Type: Grant
Filed: January 16, 1990
Date of Patent: April 2, 1991
Assignee: California Institute of Technology
Inventor: James R. Janesick

Multipinned phase charge-coupled device
Patent number: 4963952
Abstract: A back illuminated, buried channel, multiphase charge-coupled device for imaging has a photosensitive volume bounded by silicon dioxide layers on both the front and back. The dark noise generated by these interfaces with the photosensitive volume is reduced by negative bias potential pinning the front at about -6V and the back at about -0.4V. To create fixed barrier phases at the front for accumulation within each pixel comprised of multiphase gates, positive ions are implanted at one phase gate while the others are phase clocked into channel inversion. Otherwise the phase clock of at least one gate must be controlled to provide accumulation to provide a "partial-inversion" technique. The negative bias at the back may be varied to adjust the quantum efficiency of the device, thus providing electronic shuttering.
Type: Grant
Filed: March 10, 1989
Date of Patent: October 16, 1990
Assignee: California Institute of Technology
Inventor: James R. Janesick

Photosensor with enhanced quantum efficiency
Patent number: 4822748
Abstract: A method to significantly increase the quantum efficiency (QE) of a CCD (or similar photosensor) applied in the UV, far UV and low energy x-ray regions of the spectrum. The increase in QE is accomplished by overthinning the backside of a CCD substrate beyond the epitaxial interface and UV flooding the sensor prior to use. The UV light photoemits electrons to the thinned surface and charges the backside negatively. This in turn forms an accumulation layer of holes near the Si-SiO.sub.2 interface creating an electric field gradient in the silicon which directs the photogenerated signal to the frontside where they are collected in pixel locations and later transferred. An oxide film, in which the backside charge resides, must have quality equivalent to a well aged native oxide which typically takes several years to form under ambient conditions. To reduce the amount of time in growing an oxide of sufficient quality, a process has been developed to grow an oxide by using deionized steam at 95.degree. C.
Type: Grant
Filed: August 24, 1987
Date of Patent: April 18, 1989
Assignee: California Institute of Technology
Inventors: James R. Janesick, Stythe T. Elliott

CCD imaging sensors
Patent number: 4798958
Abstract: A method for promoting quantum efficiency (QE) of a CCD imaging sensor for UV, far UV and low energy x-ray wavelengths by overthinning the back side beyond the interface between the substrate and the photosensitive semiconductor material, and flooding the back side with UV prior to using the sensor for imaging. This UV flooding promotes an accumulation layer of positive states in the oxide film over the thinned sensor to greatly increase QE for either frontside or backside illumination. A permanent or semipermanent image (analog information) may be stored in a frontside SiO.sub.2 layer over the photosensitive semiconductor material using implanted ions for a permanent storage and intense photon radiation for a semipermanent storage.
Type: Grant
Filed: March 27, 1987
Date of Patent: January 17, 1989
Assignee: California Institute of Technology
Inventors: James R. Janesick, Stythe T. Elliott

Producing CCD imaging sensor with flashed backside metal film
Patent number: 4760031
Abstract: A backside illuminated CCD imaging sensor for reading out image charges from wells of the array of pixels is significantly improved for blue, UV, far UV and low energy x-ray wavelengths (1-5000.ANG.) by so overthinning the backside as to place the depletion edge at the surface and depositing a thin transparent metal film of about 10.ANG. on a native-quality oxide film of less than about 30.ANG. grown on the thinned backside. The metal is selected to have a higher work function than that of the semiconductor to so bend the energy bands (at the interface of the semiconductor material and the oxide film) as to eliminate wells that would otherwise trap minority carriers. A bias voltage may be applied to extend the frontside depletion edge to the interface of the semiconductor material with the oxide film in the event there is not sufficient thinning.
Type: Grant
Filed: March 3, 1986
Date of Patent: July 26, 1988
Assignee: California Institute of Technology
Inventor: James R. Janesick

Laser pulse detection method and apparatus
Patent number: 4669882
Abstract: A sensor is described for detecting the difference in phase of a pair of returned light pulse components, such as the two components of a light pulse of an optical gyro. In an optic gyro, the two light components have passed in opposite directions through a coil of optical fiber, with the difference in phase of the returned light components determining the intensity of light shining on the sensor. The sensor includes a CCD (charge coupled device) that receives the pair of returned light components to generate a charge proportional to the number of photons in the received light. The amount of the charge represents the phase difference between the two light components. At a time after the transmission of the light pulse and before the expected time of arrival of the interfering light components, charge accumulating in the CCD as a result of reflections from optical components in the system, are repeatedly removed from the CCD, by transferring out charges in the CCD and dumping these charges.
Type: Grant
Filed: February 22, 1984
Date of Patent: June 2, 1987
Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
Inventors: Willis C. Goss, James R. Janesick

Image sensor with deep well region and method of fabricating the image sensor
Publication number: 20050255625
Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.
Type: Application
Filed: June 14, 2005
Publication date: November 17, 2005
Inventors: James Janesick, Eugene Dines, Mark Muzilla, Maryn Stapelbroek

Image sensor with deep well region and method of fabricating the image sensor
Publication number: 20050139833
Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.
Type: Application
Filed: October 28, 2004
Publication date: June 30, 2005
Inventors: James Janesick, Eugene Dines, Mark Muzilla, Maryn Stapelbroek

Multi-mode imager with pinned photo region photoreceptors
Patent number: 6881941
Abstract: An imager includes an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. The high-light mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.
Type: Grant
Filed: November 8, 2001
Date of Patent: April 19, 2005
Assignee: ESS Technology, Inc.
Inventor: James Janesick

Multi-mode imager with pinned photo region photoreceptors
Patent number: 6765186
Abstract: An imager includes an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. The high-light mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.
Type: Grant
Filed: April 30, 2002
Date of Patent: July 20, 2004
Assignee: ESS Technology, Inc.
Inventor: James Janesick

Multi-mode imager with pinned photo region photoreceptors
Publication number: 20030085339
Abstract: An imager includes an array of imager cells coupled to a multi-mode controller. The multi-mode controller includes circuitry that implements several modes of operation, including a high-light mode, a low-light mode, and a Snap mode. The highlight mode provides charge accumulation in a photoreceptor potential well, a readout potential well, and a sense node potential well. The low-light mode provides charge accumulation in the photoreceptor potential well constrained by an integration potential well. The Snap mode of operation simultaneously transfers accumulated charge for a set of the imager cells to their sense nodes. In addition, the multi-mode controller may select one of a plurality of V+ integration voltages for setting up a selected charge capacity in one of the imager cells. Thus, the V+ integration voltage may be increased to provide charge capacity to address increased light levels.
Type: Application
Filed: April 30, 2002
Publication date: May 8, 2003
Inventor: James Janesick

MOS multi-pinned (MP) pixel
Patent number: 9287319
Abstract: A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.
Type: Grant
Filed: November 4, 2013
Date of Patent: March 15, 2016
Assignee: SRI International
Inventor: James Robert Janesick

Readout transistor circuits for CMOS imagers
Patent number: 9200956
Abstract: A readout transistor circuit for a pixel is disclosed. The readout transistor circuit includes a sense node. A reset transistor is in signal communication with the sense node. A source follower transistor is in signal communication with the sense node. A row select transistor is in signal communication with the source follower transistor. A switching transistor is in signal communication with the sense node. A capacitor is in signal communication with the switching transistor. The switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e?) ratio and a high voltage-per-charge (V/e?) to enable low noise performance of the sense node. The capacitor may be a metal-insulator-metal (MIM) capacitor. At least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor may be a MOSFET. One or more of the MOSFETs may be a buried channel MOSFET.
Type: Grant
Filed: June 27, 2011
Date of Patent: December 1, 2015
Assignee: SRI INTERNATIONAL
Inventor: James Robert Janesick

Ring pixel for CMOS imagers
Patent number: 8835999
Abstract: A CMOS pixel is disclosed. The CMOS pixel includes a semiconductor substrate; a sense node formed in the semiconductor substrate and positioned substantially in the center of the CMOS pixel; a transfer gate formed about the sense node; and at least one photodiode formed about the transfer gate. A reset transistor, a source follower transistor, and a row select transistor are located substantially to one side of the CMOS pixel substantially adjacent to the photodiode. The sense node is operable to be floating. An implant may be formed about the photodiode configured to step potential in a direction toward the sense node.
Type: Grant
Filed: July 27, 2010
Date of Patent: September 16, 2014
Assignee: SRI International
Inventor: James Robert Janesick

SOI-based CMOS imagers employing flash gate/chemisorption processing
Patent number: 8779481
Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide later is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.
Type: Grant
Filed: January 24, 2013
Date of Patent: July 15, 2014
Assignee: SRI International
Inventor: James Robert Janesick

CMOS MULTI-PINNED (MP) PIXEL
Publication number: 20140138748
Abstract: A CMOS multi-pinned pixel having very low dark current and very high charge transfer performance over that of conventional CMOS pixels is disclosed. The CMOS pixel includes epitaxial silicon and at least one transfer gate formed upon the epitaxial silicon. A pinned-photodiode is formed in the epitaxial silicon. A multi-pinned (MP) implant layer is implanted in the epitaxial silicon at least partially extending across the pinned-photodiode and substantially underlying the at least one transfer gate of the CMOS pixel to promote dark current passivation during an accumulation state and promote charge transfer during a transfer state.
Type: Application
Filed: November 4, 2013
Publication date: May 22, 2014
Applicant: SRI International
Inventor: James Robert Janesick

Substrate bias for CMOS imagers
Patent number: 8592245
Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.
Type: Grant
Filed: October 17, 2012
Date of Patent: November 26, 2013
Assignee: SRI International
Inventor: James Robert Janesick

SOI-based CMOS imagers employing flash gate/chemisorption processing
Patent number: 8389319
Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide layer is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.
Type: Grant
Filed: July 27, 2010
Date of Patent: March 5, 2013
Assignee: SRI International
Inventor: James Robert Janesick

Substrate bias for CMOS imagers
Patent number: 8319262
Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.
Type: Grant
Filed: July 27, 2010
Date of Patent: November 27, 2012
Assignee: SRI International
Inventor: James Robert Janesick

P-PIXEL CMOS IMAGERS USING ULTRA-THIN SILICON ON INSULATOR SUBSTRATES (UTSOI)
Publication number: 20120104464
Abstract: A CMOS image sensor is disclosed. The CMOS image sensor includes a semiconductor substrate having a surface. An epitaxial layer is grown on the surface. A p-type CMOS pixel formed substantially in the epitaxial layer. In one version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at a predetermined distance from the surface and which decreases monotonically on both sides of the profile from the maximum value within the semiconductor substrate and the epitaxial layer. In another version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at the surface and which decreases monotonically with increasing distance from the surface within the semiconductor substrate and the epitaxial layer.
Type: Application
Filed: October 27, 2011
Publication date: May 3, 2012
Inventors: James Robert Janesick, Peter Alan Levine, John Robertson Tower

READOUT TRANSISTOR CIRCUITS FOR CMOS IMAGERS
Publication number: 20110315854
Abstract: A readout transistor circuit for a pixel is disclosed. The readout transistor circuit includes a sense node. A reset transistor is in signal communication with the sense node. A source follower transistor is in signal communication with the sense node. A row select transistor is in signal communication with the source follower transistor. A switching transistor is in signal communication with the sense node. A capacitor is in signal communication with the switching transistor. The switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e?) ratio and a high voltage-per-charge (V/e?) to enable low noise performance of the sense node. The capacitor may be a metal-insulator-metal (MIM) capacitor. At least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor may be a MOSFET. One or more of the MOSFETs may be a buried channel MOSFET.
Type: Application
Filed: June 27, 2011
Publication date: December 29, 2011
Inventor: James Robert Janesick

SUBSTRATE BIAS FOR CMOS IMAGERS
Publication number: 20110024808
Abstract: A CMOS image sensor is disclosed. The CMOS imager includes a lightly doped semiconductor substrate of a first conductivity type. At least one CMOS pixel of a second conductivity type is formed in the semiconductor substrate. The semiconductor substrate is configured to receive a bias voltage applied for substantially depleting the semiconductor substrate and for forming a depletion edge within the semiconductor substrate. A well of the second conductivity type substantially surrounds the at least one CMOS pixel to form a depletion region about the at least one CMOS pixel operable to form a minimum predetermined barrier to the depletion edge within the semiconductor substrate to pinch off substrate bias in proximity to the return contact.
Type: Application
Filed: July 27, 2010
Publication date: February 3, 2011
Inventor: James Robert Janesick

SOI-BASED CMOS IMAGERS EMPLOYING FLASH GATE/CHEMISORPTION PROCESSING
Publication number: 20110024810
Abstract: A method of manufacturing a CMOS image sensor is disclosed. A silicon-on-insulator substrate is provided, which includes providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer. A semiconductor substrate is epitaxially grown substantially overlying the seed layer. The mechanical substrate and at least a portion of the insulator layer are removed. An ultrathin oxide layer is formed substantially underlying the semiconductor substrate. A mono layer of metal is formed substantially underlying the ultrathin oxide layer.
Type: Application
Filed: July 27, 2010
Publication date: February 3, 2011
Inventor: James Robert Janesick

RING PIXEL FOR CMOS IMAGERS
Publication number: 20110024809
Abstract: A CMOS pixel is disclosed. The CMOS pixel includes a semiconductor substrate; a sense node formed in the semiconductor substrate and positioned substantially in the center of the CMOS pixel; a transfer gate formed about the sense node; and at least one photodiode formed about the transfer gate. A reset transistor, a source follower transistor, and a row select transistor are located substantially to one side of the CMOS pixel substantially adjacent to the photodiode. The sense node is operable to be floating. An implant may be formed about the photodiode configured to step potential in a direction toward the sense node.
Type: Application
Filed: July 27, 2010
Publication date: February 3, 2011
Inventor: James Robert Janesick

Image sensor with deep well region and method of fabricating the image sensor
Patent number: 7250325
Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.
Type: Grant
Filed: June 14, 2005
Date of Patent: July 31, 2007
Assignee: Sarnoff Corporation
Inventors: James Robert Janesick, Eugene L. Dines, Mark S. Muzilla, Maryn G. Stapelbroek

Image sensor with deep well region and method of fabricating the image sensor
Patent number: 7166878
Abstract: An imager, an image sensor included in the imager and a method of fabricating the image sensor are provided. The image sensor having a substrate with front and back sides to produce image data, includes a transparent conductive coating arranged on the back side of the substrate, a first well region of a first conductive type having first and second opposite sides, the first side being arranged adjacent with the front side of the image sensor; and a second well region of a second conductive type, different from the first conductive type and having a deep well region provided adjacent with the second side of the first well region, the transparent conductive coating configured to develop or to receive a first potential and the first well region configured to receive a second potential to substantially deplete a region between the transparent conductive coating and the first well region.
Type: Grant
Filed: October 28, 2004
Date of Patent: January 23, 2007
Assignee: Sarnoff Corporation
Inventors: James Robert Janesick, Eugene L. Dines, Mark S. Muzilla, Maryn G. Stapelbroek

Imager cell with pinned transfer gate
Patent number: 6909126
Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is tied to the same potential of a substrate of the imager cell and is disposed between the photoreceptor and the sense node in order to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. According to various embodiments of the invention, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.
Type: Grant
Filed: January 24, 2002
Date of Patent: June 21, 2005
Assignee: ESS Technology, Inc.
Inventor: Jim Janesick

Imager cell with pinned transfer gate
Patent number: 6762441
Abstract: An imager cell includes a photoreceptor, a sense node, and a pinned transfer gate. The pinned transfer gate is disposed to transfer charge between the photoreceptor and the sense node. The imager further includes a reset transistor disposed to reset the sense node, and an output amplifier coupled to the sense node. Control circuitry supplies a photoreceptor readout clock to the photoreceptor. The readout clock includes an integration period and a transfer period. During the integration period, the readout clock is at an integration voltage V+ which may be varied to setup a desired charge capacity in the photoreceptor. A thin gate structure or light aperture may be included to enhance blue light response of the photoreceptor. Thus, the imager cell provides improved noise performance, selective charge capacities, and improved blue light response beyond that of conventional imager cells.
Type: Grant
Filed: October 15, 2001
Date of Patent: July 13, 2004
Assignee: ESS Technology, Inc.
Inventor: Jim Janesick